In the semiconductor manufacturing industry, photoresist materials are used for transferring an image to one or more underlying layer, such as metal, semiconductor and dielectric layers, disposed on a semiconductor substrate, as well as to the substrate itself. To increase the integration density of semiconductor devices and allow for the formation of structures having dimensions in the nanometer range, photoresists and photolithography processing tools having high-resolution capabilities have been and continue to be developed.
Positive-tone chemically amplified photoresists are conventionally used for high-resolution processing using a positive tone development (PTD) process. In the PTD process, exposed regions of a photoresist layer are soluble in a developer solution, typically an aqueous alkaline developer, and are removed from the substrate surface, whereas unexposed regions which are insoluble in the developer remain after development to form a positive image. To improve lithographic performance, immersion lithography tools have been developed to effectively increase the numerical aperture (NA) of the lens of the imaging device, for example, a scanner having a KrF or ArF light source. This is accomplished by use of a relatively high refractive index fluid (i.e., an immersion fluid) between the last surface of the imaging device and the upper surface of the semiconductor wafer.
Considerable effort has been made to extend the practical resolution beyond that achieved with positive tone development from both a materials and processing standpoint. One such example is the negative tone development (NTD) process. The NTD process allows for improved resolution and process window as compared with standard positive tone imaging by making use of the superior imaging quality obtained with bright field masks for printing critical dark field layers. NTD resists typically employ a resin having acid-labile (also referred to herein as acid-cleavable) groups and a photoacid generator. Exposure to actinic radiation causes the photoacid generator to form an acid which, during post-exposure baking, causes cleavage of the acid-labile groups giving rise to a polarity switch in the exposed regions. As a result, a difference in solubility characteristics is created between exposed and unexposed regions of the resist such that unexposed regions of the resist can be removed by organic solvent developers, leaving behind a pattern created by the insoluble exposed regions.
To further extend resolution capabilities beyond those typically obtained with standard resist patterning techniques, various processes for pattern shrink have been proposed. These processes involve increasing the effective thickness of the resist pattern sidewalls to reduce (i.e., “shrink”) the spacing, for example, between adjacent lines or within a trench or hole pattern. In this way, features such as trenches and contact holes formed from the patterns can be made smaller. Known shrink techniques include, for example, chemical vapor deposition (CVD) assist, acid diffusion resist growth, thermal flow and polymer blend self-assembly.
The CVD assist shrink process (see K. Oyama et al, “The enhanced photoresist shrink process technique toward 22 nm node”, Proc. SPIE 7972, Advances in Resist Materials and Processing Technology XXVIII, 79722Q (2011)), uses a CVD-deposited layer formed over a photoresist pattern including, for example, contact hole, line/space or trench patterns. The CVD material is etched back, leaving the material on sidewalls of the resist pattern. This increases the effective lateral dimensions of the resist pattern, thereby reducing the open areas that expose the underlying layer to be etched. The CVD assist shrink technique requires use of CVD and etching tools which are costly, add to the complexity of the process and are disadvantageous in terms of process throughput.
In the acid diffusion resist growth process, also referred to as the RELACS process (see L. Peters, “Resists Join the Subλ, Revolution”, Semiconductor International, 1999. 9), an acid-catalyzed crosslinkable material is coated over a PTD-generated resist patterned surface. Crosslinking of the material is catalyzed by an acid component present in the resist pattern that diffuses into the crosslinkable material during a baking step. The crosslinking takes place in the material in the vicinity of the resist pattern in the acid diffusion region to form a coating on sidewalls of the pattern, thereby reducing the lateral dimension of open areas of the pattern. This process typically suffers from iso-dense bias (IDB), wherein growth of the crosslinked layer on the resist pattern occurs non-uniformly across the die surface depending on density (spacing between) adjacent resist patterns. As a result, the extent of “shrink” for identical features can vary across die based on pattern density. This can lead to patterning defects and variations in electrical characteristics across the die for what are intended to be identical devices.
Polymer blend self-assembly (see Y. Namie et al, “Polymer blends for directed self-assembly”, Proc. SPIE 8680, Alternative Lithographic Technologies V, 86801M (2013)) involves coating a composition containing an immiscible blend of hydrophilic and hydrophobic polymers over the photoresist pattern. The composition is then annealed, causing the polymers to phase separate, wherein the hydrophilic polymer preferentially segregates to the resist pattern sidewalls and the hydrophobic polymer fills the remainder of the volume between the resist pattern sidewalls. The hydrophobic polymer is next removed by solvent development, leaving the hydrophilic polymer on the resist pattern sidewalls. Polymer blend self-assembly has been found to suffer from proximity and size effects. As the shrink ratio is determined by the volume ratio of the two polymers, all features shrink by the same relative percentage rather than by the same absolute amount. This can lead to the same problems described with respect to the acid diffusion resist growth technique.
There is a continuing need in the art for improved pattern treatment methods and pattern treatment compositions which address one or more problems associated with the state of the art and which allow for the formation of fine patterns in electronic device fabrication.